The Open Cybernetics & Systemics Journal

2014, 8 : 17-21
Published online 2014 September 16. DOI: 10.2174/1874110X01408010017
Publisher ID: TOCSJ-8-17

Configurable Verification Stimulus Acceleration Method Based on Multicore Processor

Pan Guoteng , Tang Yuxing , Ou Guodong , Luo Li and Yang Qingna
College of Computer, National University of Defense Technology, Changsha 410073, Hunan, China.

ABSTRACT

Functional verification has become a major challenge in the chip design area. To improve the efficiency of verification, it is necessary to choose appropriate verification method and tools. An important aspect of functional verification is RTL verification, simulation-based verification is main method in RTL verification. Based on FT-8 multicore processor, we developed a configurable test stimulus acceleration method, loading the test stimulus into memory and L2 cache to speed up the processor instructions fetch, which can shorten simulation cycle and simulation time, reduce the verification cost and guaranteed the correctness of design.

Keywords:

Acceleration, multicore processor, simulation-based verification, test stimulus.