Hardware Implementation of AES Encryption and Decryption System Based on FPGA

ABSTRACT

AES algorithm has played an important role in information security field for a long time since Rijndael algorithm was announced as advanced encryption standard. Hardware implementation based on FPGA of AES algorithm has the advantages of fast, flexible, short development cycle, etc. Hardware implementation based on FPGA of AES encryption and decryption system was studied in detail in this paper. First, implementation scheme and key technology to adopt internal and external mixing pipeline structure were determined, and the overall design flow chart was given. Next, this design supports three modes of encryption and decryption process of AES algorithm under the condition of data group of 128 bits, key length of 128, 192 and 256 bits respectively. In the following, system optimization design of AES encryption and decryption algorithm was completed on the same piece of FPGA chip; Finally, coding work and comprehensive compilation were finished by QUARTUS II development tool, and the simulation results by MODELSIM software were also given. In a word, this design realized the balance of resources and speed to a bigger extent.

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