Power-Gating Single-Rail MOS Current-Mode Logic Circuits Using High Threshold PMOS Transistors as Linear Resistors

ABSTRACT

In this paper, a power-gating technology for single-rail MOS Current Mode Logic (SRMCML) circuits is presented, which use the high-threshold PMOS transistors as linear load resistors to reduce the power dissipation in the sleep mode. The basic SRMCML cells, such as buffer/inverter, AND2/NAND2, AND3/NAND3, OR2/NOR2, OR3/NOR3, XOR2/XNOR2, multiplexer, and 1-bit full adder, are used to verify the effectiveness of the proposed power-gating scheme. The equivalent model for calculating energy dissipations of the power-gating SRMCML circuits is constructed. All circuits are simulated with HSPICE at a 130 nm CMOS process. By simulating power-gating SRMCML circuits in active and sleep modes, it is concluded that the power dissipation of power-gating SRMCML circuits in sleep mode is reduced with the decrease of the device sizes of high-threshold PMOS sleep transistors, while the power dissipation of power-gating SRMCML circuits is almost independent of the device sizes of sleep transistors in active mode. The power dissipation comparisons among power-gating SRMCML, conventional SRMCML, and power-gating static CMOS circuits are carried out. The power dissipation of the proposed power-gating SRMCML circuits is the least among the three above mentioned structures.

Keywords:

Energy-efficient design, high-speed digital circuit, modeling optimizing of sleep transistors, MOS current mode logic, power-gating technology.