The Open Electrical & Electronic Engineering Journal
2008, 2 : 56-61Published online 2008 July 10. DOI: 10.2174/1874129000802010056
Publisher ID: TOEEJ-2-56
Optimum Design for Eliminating Back Gate Bias Effect of Silicon-on-insulator Lateral Double Diffused Metal-oxide-semiconductor Field Effect Transistor with Low Doping Buried Layer
Department of Electrical
Engineering, National Central University, R.O.C., Taiwan.
ABSTRACT
An optimum design with silicon-on-insulator (SOI) device structure was proposed to eliminate back gate bias effect of the lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) and to improve breakdown voltage. The SOI structure was characterized by low doping buried layer (LDBL) inserted between the silicon layer and the buried oxide layer. The LDBL thickness is a key parameter to affect the strong inversion condition in the back MOS capacitor of the new SOI diode. The optimum design of LDBL thickness for the SOI diode was 2.65 μm. Furthermore, the breakdown capability has been improved 11%.