Pseudo-Failure Impacts on ESD Robustness in Integrated Circuits I/O Ports by the Parasitic Capacitance

ABSTRACT

Semiconductor components are commonly electrostatic discharge (ESD) sensitive. The ESD event would usually cause a harm or destruction of the devices. Due to the requirement of circuits' reliability, the test for ESD robustness is necessary for almost all the product of integrated circuits. But during the test of ESD zapping, the test pin may temporary store ESD zapping charges. These stored charges will temporary cause shifting of the I-V characteristic curve of the test pin. And, it will seriously influence the ESD test results. Therefore, the electrostatic discharge (ESD) properties of the IC products in terms of the internal parasitic capacitance of the test pin are investigated in this paper. Eventually, it is found if the parasitic capacitance of the test pin is over 10-pf, the ESD test results may be not correct. We find, by suitable adjustment, the delay time between the ESD zapping and the measurement of I-V characteristic curve, a more correct result can be obtained. Therefore, it can correct the mistake made by parasitic capacitance in ICs and have a reliable ESD test result.

Keywords:

Electrostatic discharge (ESD), ESD failure threshold (VESD), human-body model (HBM), parasitic capacitance, positive-to-VSS (PS) mode, pseudo failure.