An Investigation of Super-Threshold FinFET Logic Circuits Operating on Medium Strong Inversion Regions

ABSTRACT

Scaling supply voltage of FinFET circuits is an efficient method to achieve low power dissipation. Superthreshold FinFET logic circuits can attain low power consumption with favorable performance, because FinFET devices operating on medium strong inversion regions can provide better drive strength than conventional CMOS transistors. The supply voltage of the super-threshold circuit is much larger than threshold voltage of the transistors, but it is lower than normal standard supply voltage. In this paper, basic FinFET logic gates based on static logic, DCVSL (Differential Cascode Voltage Switch Logic), PTL (Pass Transistor Logic), and TG (Transmission Gate) logic styles operating on medium strong inversion regions are investigated in terms of power consumption and delay. All circuits are simulated with HSPICE at a PTM (Predictive Technology Model) 32nm FinFET technology. The simulation results show that superthreshold FinFET logic gates operating on medium strong inversion regions attain about 41% power reduction with a penalty of only about 23%.

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